Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to an apparatus and method for synchronizing and clocks and data related to the transmission and reception of source synchronous signals.
Description of the Related Art
A present day computer system employs a source synchronous system bus to provide for exchange of data between bus agents, such as between a microprocessor and a memory hub. A “source synchronous” bus protocol allows for the transfer of data at very high bus speeds. Source synchronous protocols operate on the principle that a transmitting bus agent places data out on the bus for a fixed time period and asserts or switches a “strobe” signal corresponding to the data to indicate to a receiving bus agent that the data is valid. Both data signals and their corresponding strobe are routed over the bus along equal propagation paths (both physically and electromagnetically), thus enabling a receiver to be relatively certain that when switching of the corresponding strobe is detected, data is valid on the data signals. For purposes of the present invention, a bus agent may be any electronic element that utilizes source synchronous signaling for the transfer of data to/from another bus agent over a source synchronous bus. Exemplary bus agents may be, but are not limited to, central processing units (CPUs), microprocessors, memory controllers, memory hubs, chipsets, and graphics controllers. The source synchronous bus may also be known as a system bus, a front side bus, or a back side bus. Bus agents may be individually packaged, disposed on a motherboard, and interconnected by conductive traces on the motherboard. Additionally, a plurality of bus agents may be disposed within the same package that is mounted to a motherboard, where the plurality of bus agents may be individual dies within the package or they may be integrated into the same integrated circuit die and are interconnected via traces on the die.
Yet, source synchronous data strobes and data signals are subject to error for a number of different reasons. These inaccuracies may be the result of uncontrollable design margins, fabrication tolerances, or environmental factors such as voltage or temperature. In most cases, it is desired that a strobe signal switch precisely halfway through a data validity period so that there is equal set up and hold time for the data as seen at the receiver. However, inaccuracies resulting from the above factors may result in skewing of the data signals and/or their strobes such that reception conditions are not optimum. Consequently, operating frequency of associated devices is limited.
Another source of error may be caused by distribution of a strobe signal within a receiving device. While system designers go to great lengths to ensure that a strobe and its associated data signals are routed along the same propagation path on a system board (or, motherboard), it is well known that once the strobe enters the receiving device, it must be distributed to all of the internal synchronous receivers that are associated with that strobe. Some techniques for distributing a strobe signal to internal receivers simply adds propagation lengths that are required to route the strobe to the internal receivers, which may add delay over that of the data signals, thereby skewing the phase of the synchronous transmission. More recent mechanisms for strobe distribution also introduce buffering of the disturbed strobe signals, thereby skewing the phase of the synchronous transmission even more.
Therefore, what is needed are apparatus and methods that compensate for misalignment of signals and strobes on a source synchronous data bus, thus allowing optimization of a device's operating frequency.
What is also needed is a technique that allows the signals on a synchronous bus to be optimized for reception by modifying the phase alignment of a data strobe and its corresponding data signals.
What is furthermore needed is an automatic mechanism that allows the phase alignment of a data strobe and its associated data signals to be dynamically optimized at a receiving device.
What is moreover needed is an apparatus that is programmable at the motherboard level to compensate for fabrication and design inaccuracies, voltage variations, and temperature variations in an automated signal alignment mechanism.
What is additionally needed is a synchronous receiver that automatically compensates for misalignment of signals on a source synchronous data bus.